1. Field
Exemplary embodiments of the present invention relate to a test of semiconductor chips, and more particularly, to an apparatus and method for simultaneously testing a plurality of chips.
2. Description of the Related Art
A multi-test for connecting a plurality of semiconductor chips (e.g., a few tens to a few hundreds of semiconductor chips) to one piece of test equipment and testing the chips is performed in semiconductor fields. Data for testing is provided from the test equipment. The provided test data is simultaneously written in memory cells of a plurality of memory banks included in each of the chips. The presence of a defect of the chips can be checked by simultaneously reading the data written as described above.
Since the multi-test is simultaneously performed with respect to a plurality of banks, write drivers provided corresponding to the respective banks and input buffers provided in a chip are driven at the same time. As the write drivers and the input buffers are simultaneously driven as described above, instantaneous current consumption may be increased, and an excessive load may be applied to the test equipment. Therefore, a method that reduces current consumption in a multi-test of semiconductor chips may be useful.